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The original Verilog simulator, Gateway Design's Verilog-XL was the first (and only, for a time) Verilog simulator to be qualified for ASIC (validation) sign-off. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995.
List of free analog and digital electronic circuit simulators, available for Windows, macOS, Linux, and comparing against UC Berkeley SPICE. The following table is split into two groups based on whether it has a graphical visual interface or not. The later requires a separate program to provide that feature, such as Qucs-S, [1] Oregano, [2] or ...
Icarus Verilog is an implementation of the Verilog hardware description language compiler that generates netlists in the desired format and a simulator. It supports the 1995, 2001 and 2005 versions of the standard, portions of SystemVerilog , and some extensions.
VHDL analyzer, compiler, and simulator. [12] Icarus Verilog *BSD, Linux, Mac: GPL-2.0-or-later: Verilog simulator Verilator: Posix: LGPL-3.0-only or Artistic-2.0: Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog into cycle accurate C++ or SystemC code following 2-state
Quite Universal Circuit Simulator (Qucs) is a free-software electronics circuit simulator software application released under GPL. It offers the ability to set up a circuit with a graphical user interface and simulate the large-signal, small-signal and noise behaviour of the circuit. Pure digital simulations are also supported using VHDL and/or ...
Verilator is a free and open-source software tool which converts Verilog (a hardware description language) to a cycle-accurate behavioral model in C++ or SystemC.The generated models are cycle-accurate and 2-state; as a consequence, the models typically offer higher performance than the more widely used event-driven simulators, which can model behavior within the clock cycle.
SystemVerilog. SystemVerilog, standardized as IEEE 1800, is a hardware description and hardware verification language used to model, design, simulate, test and implement electronic systems. SystemVerilog is based on Verilog and some extensions, and since 2008, Verilog is now part of the same IEEE standard.
SPICE OPUS. SPICE OPUS is a free general purpose electronic circuit simulator, developed and maintained by members of EDA Group, University of Ljubljana, Slovenia. [1] It is based on original Berkeley ’s SPICE analog circuit simulator and includes various improvements and advances, such as memory-leak bug fixes and plotting tool improvements.